1. Field of the Invention
Embodiments of the present invention generally relate to etch processes, and more specifically, to controlling an etch profile of an organic material.
2. Description of the Related Art
In the field of semiconductor device fabrication, as device feature sizes decrease to 0.18 μm and smaller, RC delay of interconnects becomes a major limiting factor for device speed. Two areas of development focus on this problem. First, the interconnect conductor resistance is being reduced by the use of copper and other conductors having a lower resistance than aluminum, which has been the industry standard for conductive interconnect material. In the second area, the interconnect contribution to the capacitance is being reduced by the use of dielectric materials having a lower dielectric constant (k) than silicon dioxide, which has been the industry standard dielectric.
Unfortunately, such lower dielectric constant (or low-k) materials are not easy to process using conventional fabrication techniques. For example, when etching low-k materials, it can be very difficult to satisfactorily control the etch profile of features being formed in the low-k materials. Other difficulties in etching low-k materials include undesirable micro-loading, micro-trenching, critical dimensions (CD) and poor sidewall profile.
Thus, there is a need for an improved method for etching organic materials.